Differential transceivers are known in the art. Differential transceivers can be configured as monolithic integrated circuits designed for bi-directional data communications. Differential transceivers are generally used in high performance systems where maximum signal frequency is desired. For example, differential transceivers can be utilized in high performance applications including Low Voltage Differential Signalling (LVDS) and Pseudo Emitter Coupled Logic (PECL) applications.
Referring to FIG. 1, a conventional differential transceiver 10 is shown. Differential transceiver 10 includes plural input/output (I/O) pads 11, 12. Differential transceiver 10 additionally includes parallel MOS devices 13, 14 coupled with ground via a series MOS device 15. Parallel MOS devices 13, 14 are coupled with respective inputs 11, 12. Plural control lines 16, 17, 18 are utilized to control gates of respective MOS devices 13, 14, 15.
It is generally recognized that some semiconductor devices are susceptible to damage from electrical overstress (EOS) conditions. These conditions occur when the voltage or amperage ratings for a circuit are exceeded. Exemplary electrical overstress conditions include electrostatic discharge (ESD), transient conditions, latch-up, incorrect polarity connections, etc. The electrical overstress conditions are characterized by over-voltage and over-current stress events. Electrical overstress events can permanently damage integrated circuitry rendering a semiconductor device inoperable.
Accordingly, it is highly desired to protect semiconductor devices from electrostatic discharge and other electrical overstress conditions. Some solutions have attempted to minimize the accumulation of electrostatic charge to prevent electrostatic discharge. Exemplary solutions have included utilization of protective clothing such as shoes, smocks, etc. for workers in the semiconductor industry. Such approaches may alleviate the problem of electrostatic discharge to some extent, but consumers may not be aware of the potential damaging effects of electrostatic discharge upon the electronic components being handled.
In an effort to reduce effects from overstress events, conventional designs have added protection circuits 19, 20 in parallel with inputs 11, 12 as illustrated in FIG. 1. Exemplary protection devices 19, 20 include NMOS ESD protection circuitry added in parallel to the I/O connections 11, 12 of differential transceiver 10.
Implementing electrostatic discharge protection circuitry as illustrated in FIG. 1 has the drawback of adding capacitance to I/O pins 11, 12. Such additional capacitance is detrimental to high frequency signalling and degrades the performance of differential transceiver 10. This protection scheme is not appropriate in high performance applications such as LVDS and PECL.
Various approaches in the art have therefore been aimed at minimizing the capacitance added by ESD protection devices 19, 20. Exemplary ESD protection structures 19, 20 having minimal capacitance include low voltage semiconductor controlled rectifiers (SCR).
Other conventional constructions of differential transceivers provide MOS device 15 separated from the differential pair of MOS devices 13, 14. Separated differential transceiver constructions require other types of protection circuitry for adequate overstress event protection but suffer from the corresponding degradation of performance.
Therefore, there exists a need in the art to provide a differential device which overcomes the problems associated with the prior art devices and can be utilized in high performance applications.